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| 7544 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0012-0104Z Rev.1.04 2004.06.08 DESCRIPTION The 7544 Group is the 8-bit microcomputer based on the 740 family core technology. The 7544 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A/D converter, and is useful for control of home electric appliances and office automation equipment. * * * FEATURES * * * * * * * * Basic machine-language instructions ...................................... 71 The minimum instruction execution time ......................... 0.25 s (at 8 MHz oscillation frequency, double-speed mode for the shortest instruction) Memory size ROM ......................................................... 8 K bytes RAM ........................................................ 256 bytes Programmable I/O ports ........................................................... 25 Interrupts ................................................. 12 sources, 12 vectors Timers ............................................................................. 8-bit 2 ...................................................................................... 16-bit 1 Serial I/O ...................... 8-bit 1 (UART or Clock-synchronized) A/D converter ................................................. 8-bit 6 channels * * Clock generating circuit ............................................. Built-in type (low-power dissipation by an on-chip oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) Watchdog timer ............................................................ 16-bit 1 Power source voltage XIN oscillation frequency at ceramic/quartz-crystal oscillation, in double-speed mode At 8 MHz .................................................................... 4.5 to 5.5 V XIN oscillation frequency at ceramic/quartz-crystal oscillation, in high-speed mode At 8 MHz .................................................................... 4.0 to 5.5 V XIN oscillation frequency at RC oscillation At 4 MHz .................................................................... 4.0 to 5.5 V Power dissipation ........................................... 22.5mW(standard) Operating temperature range ................................... -20 to 85 C APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P11/TXD P10/RXD P07(LED7) P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 P37(LED13)/INT0 P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8) Package type : 32P4B Fig. 1 Pin configuration (32P4B type) M37544M2-XXXSP M37544G2SP Rev.1.04 2004.06.08 REJ03B0012-0104Z page 1 of 66 7544 Group 20 22 24 21 19 P07(LED7) P10/RXD P11/TXD P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1 23 18 17 P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 P37(LED13)/INT0 25 26 27 28 29 30 31 32 1 3 2 4 5 6 7 8 16 15 14 M37544M2-XXXGP M37544G2GP 13 12 11 10 9 P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8) VSS XOUT XIN Package type : 32P6U-A Fig. 2 Pin configuration (32P6U-A type) P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 NC NC NC NC VREF RESET CNVSS Vcc XIN XOUT VSS P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P13/SRDY P12/SCLK P11/TXD P10/RXD P07(LED7) P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 NC P37(LED13)/INT0 NC NC P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8) Package type: 42S1M Fig. 3 Pin configuration (42S1M type) M37544RSS Rev.1.04 2004.06.08 REJ03B0012-0104Z page 2 of 66 7544 Group P00(LED0)/CNTR1 P03(LED3)/TXOUT P37(LED13)/INT0 P05(LED5) P04(LED4) P02(LED2) P01(LED1) P34(LED12)/INT1 27 26 25 24 23 22 21 20 19 P06(LED6) P07(LED7) P10/RxD P11/TxD P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 N.C.: Non Connection Note: Only ES version (MP: no plan) 18 17 16 [N.C.] P33(LED11) P32(LED10) P31(LED9) P30(LED8) Vss XOUT XIN [N.C.] M37544M2-XXXHP 15 14 M37544G2HP (Note) [N.C.] 13 12 11 10 Vcc P22/AN2 P23/AN3 P24/AN4 P25/AN5 Package type: 36PJW-A Fig. 4 Pin configuration (36PJW-A type) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 3 of 66 RESET CNVss [N.C.] VREF 7544 Group FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B) Clock input X IN VSS VCC CNVSS 12 13 11 16 Clock output X OUT Reset input RESET 10 22 21 20 19 18 17 987654 3 2 1 32 31 30 29 28 27 26 25 24 23 VREF I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wakeup Rev.1.04 2004.06.08 REJ03B0012-0104Z FUNCTIONAL BLOCK 14 15 Fig. 5 Functional block diagram (32P4B package) page 4 of 66 CPU Clock generating circuit RAM Prescaler 1 (8) X Y Prescaler X (8) S CNTR0 ROM A Timer 1 (8) Timer X (8) TXOUT PCH PS PCL Timer A (16) CNTR1 Watchdog timer Reset 0 A/D converter (8) SI/O(8) INT INT 1 0 P3(6) P2(6) P1(5) P0(8) 7544 Group FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U) Clock input Clock output Reset input VSS 11 8 6 7 X IN X OU VCC CNVSS RESET 5 17 16 15 14 13 12 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 VREF I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wakeup Rev.1.04 2004.06.08 REJ03B0012-0104Z CPU 9 T 10 Fig. 6 Functional block diagram (32P6U package) page 5 of 66 Clock generating circuit RAM Prescaler 1 (8) X Y S PC H PS PCL Prescaler X (8) CNTR0 ROM A Timer 1 (8) Timer X (8) TXOUT Watchdog timer Reset Timer A (16) CNTR1 0 A/D converter (8) SI/O(8) INT0 INT1 P3(6) P2(6) P1(5) P0(8) 7544 Group FUNCTIONAL BLOCK DIAGRAM (Package: 36PJW) Clock input Clock output X IN X OUT VSS 13 8 6 7 VCC Reset input RESET CNVSS INT0 INT 1 P3 (6) P2 (6) P1(5) P0(8) 5 21 20 17 16 15 14 4 3 2 1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VREF I/O port P3 I/O port P2 I/O port I/O port P0 Key-on wakeup Rev.1.04 2004.06.08 REJ03B0012-0104Z CPU 11 12 Fig. 7 Functional block diagram (36PJW package) page 6 of 66 Clock generating circuit RAM Prescaler 1 (8) X Y Prescaler X (8) CNTR 0 ROM A Timer 1 (8) Timer X (8) TXou t S PC H PS PCL Timer A (16) CNTR 1 Watchdog timer Reset 0 A/D converter (8) SI/ O(8) 7544 Group PIN DESCRIPTION Table 1 Pin description Pin Name Vcc, Vss VREF CNVss ______ RESET XIN XOUT Power source Function *Apply voltage of 4.0 to 5.5 V to Vcc, and 0 V to Vss. Function expect a port function Analog reference *Reference voltage input pin for A/D converter voltage CNVss Reset input Clock input *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins. *For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * When the on-chip oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open. Clock output P00/CNTR1 P01 P02 P03/TXOUT P04-P07 I/O port P0 *8-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *P0 can output a large current for driving LED. *Whether a built-in pull-up resistor is to be used or not can be determined by program. * Key-input (key-on wake up interrupt input) pins * Timer X and timer A function pin P10/RxD P11/TxD P12/SCLK ____ P13/SRDY P14/CNTR0 I/O port P1 *5-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *CMOS/TTL level can be switched for P10 and P12 *6-bit I/O port having almost the same function as P0 *CMOS compatible input level *CMOS 3-state output structure *6-bit I/O port * Serial I/O function pin * Timer X function pin * Input pins for A/D converter P20/AN0-P25/AN5 I/O port P2 P30-P33 I/O port P3 *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level (CMOS/TTL level can be switched for P34 and P37). *CMOS 3-state output structure *P3 can output a large current for driving LED. P34/INT1 P37/INT0 *Whether a built-in pull-up resistor is to be used or not can be determined by program. * Interrupt input pins Rev.1.04 2004.06.08 REJ03B0012-0104Z page 7 of 66 7544 Group GROUP EXPANSION We are planning to expand the 7544 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU . Memory size ROM/PROM size .............................................................. 8 K bytes RAM size ......................................................................... 256 bytes Package 32P4B .................................................. 32-pin plastic molded SDIP 32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP 36PJW-A ...................... 0.5 mm-pitch 36-pin plastic molded SSOP 42S1M .................................... 42-pin shrink ceramic PIGGY BACK ROM size (bytes) M37544M2 8K M37544G2 0 256 RAM size (bytes) Fig. 8 Memory expansion plan Currently supported products are listed below. Table 2 List of supported products Part number M37544M2-XXXSP M37544M2-XXXGP M37544M2-XXXHP M37544G2SP M37544G2GP M37544G2HP (Note) M37544RSS Note: Only ES version (MP: no plan) 256 42S1M Emulator MCU (P) ROM size (bytes) RAM size ROM size for User () (bytes) 8192 (8062) 256 Package 32P4B 32P6U-A 36PJW-A 32P4B 32P6U-A 36PJW-A Mask ROM version Mask ROM version Mask ROM version One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (blank) Remarks Rev.1.04 2004.06.08 REJ03B0012-0104Z page 8 of 66 7544 Group FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig. 10. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 b0 A b7 b0 Accumulator Index Register X b0 X b7 Y b7 b0 Index Register Y Stack Pointer b0 S b15 b7 PCH b7 PCL b0 Program Counter N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 9 740 Family CPU register structure Rev.1.04 2004.06.08 REJ03B0012-0104Z page 9 of 66 7544 Group On-going Routine Interrupt request (Note) Execute JSR M (S) Store Return Address on Stack (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1) M (S) (S) M (S) (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1) (PS) (S - 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S) I Flag "0" to "1" Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Note : The condition to enable the interrupt Interrupt enable bit is "1" Interrupt disable flag is "0" Fig. 10 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.1.04 2004.06.08 REJ03B0012-0104Z page 10 of 66 7544 Group Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Rev.1.04 2004.06.08 REJ03B0012-0104Z page 11 of 66 7544 Group [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 8016) Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 01 Not available 10 11 Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic/quartz-crystal or RC oscillation enabled 1 : Ceramic/quartz-crystal or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic/quartz-crystal oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f() = f(XIN) (Double-speed mode)(Note 2) Note 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37544RSS".) 2: These bits are used only when a ceramic/quartz-crystal oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 11 Structure of CPU mode register After releasing reset Start with an on-chip oscillator Switch the oscillation mode selection bit (bit 5 of CPUM) An initial value is set as a ceramic/quartz-crystal oscillation mode. When it is switched to an RC oscillation, its oscillation starts. Wait by on-chip oscillator operation until establishment of oscillator clock When using a ceramic/quartz-crystal oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Select 1/1, 1/2, 1/8 or on-chip oscillator. Main routine Fig. 12 Switching method of CPU mode register Rev.1.04 2004.06.08 REJ03B0012-0104Z page 12 of 66 7544 Group Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Note on use The content of RAM is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 000016 SFR area 004016 010016 Zero page RAM RAM area RAM capacity (bytes) address XXXX16 XXXX16 Reserved area 044016 Disable YYYY16 Reserved ROM area (128 bytes) 256 013F16 ZZZZ16 ROM ROM area ROM capacity (bytes) address YYYY16 address ZZZZ16 FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page 8192 E00016 E08016 Fig. 13 Memory map diagram Rev.1.04 2004.06.08 REJ03B0012-0104Z page 13 of 66 7544 Group 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Prescaler 1 (PRE1) Timer 1 (T1) Reserved Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register1 (TCSS1) Timer count source set register2 (TCSS2) Reserved Reserved Reserved Reserved A/D control register (ADCON) A/D register (AD) Reserved Reserved MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Note : Do not access to the SFR area including nothing. Fig. 14 Memory map of special function register (SFR) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 14 of 66 7544 Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. [Pull-up control register] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P34, and P37 by program. b7 b0 Pull-up control register (PULL: address 001616, initial value: 0016) P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 - P07 pull-up control bit P30 - P33 pull-up control bit P34 pull-up control bit Disable P37 pull-up control bit 0 : Pull-up Off 1 : Pull-up On Note : Pins set to output ports are disconnected from pull-up control. Fig. 15 Structure of pull-up control register b7 b0 Port P1P3 control register (P1P3C: address 001716, initial value: 0016) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P34/INT1 input level selection bit 0 : CMOS level 1 : TTL level P10,P12 input level selection bit 0 : CMOS level 1 : TTL level Disable Fig. 16 Structure of port P1P3 control register Rev.1.04 2004.06.08 REJ03B0012-0104Z page 15 of 66 7544 Group Table 5 I/O port function table Pin P00/CNTR1 P01 P02 P03/TXOUT P04-P07 P10/RxD P11/TxD P12/SCLK ____ P13/SRDY P14/CNTR0 P20/AN0- P25/AN5 P30-P33 P34/INT1 P37/INT0 I/O port P2 I/O port P3 External interrupt input Name Input/output I/O format Non-port function Key input interrupt Timer X function output Timer A function input Related SFRs Pull-up control register Timer X mode register Timer A mode register Interrupt edge selection register Serial I/O control register Port P1,P3 control register Diagram No. (1) (2) (3) I/O port P0 I/O individual *CMOS compatible bits input level *CMOS 3-state output (Note) I/O port P1 Serial I/O function input/output (4) (5) (6) (7) (8) (9) (10) (11) Timer X function input/output A/D conversion input Timer X mode register A/D control register Pull-up control register Interrupt edge selection register Pull-up control register Port P1,P3 control register Note : Ports P10, P12, P34, and P37 are CMOS/TTL level. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 16 of 66 7544 Group (1)Port P00 Pull-up control Direction register (2)Ports P01,P02,P04-P07 Pull-up control Direction register Data bus Port latch Data bus Port latch CNTR1 interrupt input To key input interrupt generating circuit P00 key-on wakeup selection bit To key input interrupt generating circuit (3)Port P03 Pull-up control Direction register (4)Port P10 Serial I/O enable bit Receive enable bit Direction register Data bus Port latch P10, P12 input level selection bit P03/TXOUT output valid Serial I/O input Data bus Port latch Timer output * To key input interrupt generating circuit (5)Port P11 P11/TxD P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register (6)Port P12 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Data bus Port latch P10, P12 input level selection bit Serial I/O output Serial I/O clock output Serial I/O clock input * * P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 17 Block diagram of ports (1) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 17 of 66 7544 Group (7) Port P13 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register (8) Port P14 Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output CNTR0 interrupt input Serial I/O ready output (9) Ports P20-P25 Direction register (10) Ports P30-P33 Pull-up control Direction register Data bus Port latch Data bus Port latch A/D converter input Analog input pin selection bit (11) Ports P34, P37 Pull-up control Direction register Data bus Port latch P3 input level selection bit INT interrupt input * * P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 18 Block diagram of ports (2) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 18 of 66 7544 Group Interrupts Interrupts occur by 12 different sources : 5 external sources, 6 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. Table 6 Interrupt vector address and priority Interrupt source Priority Reset (Note 2) Serial I/O receive Serial I/O transmit INT0 INT1 Key-on wake-up CNTR0 CNTR1 Timer X Reserved area Reserved area Timer A Reserved area A/D conversion Timer 1 Reserved area BRK instruction 1 2 3 4 5 6 7 8 9 -- -- 10 -- 11 12 -- 13 Vector addresses (Note 1) High-order FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 Low-order FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 [Interrupt edge selection register] INTEDGE The valid edge of external interrupt INT0 and INT1 can be selected by the interrupt edge selection bit, respectively. By the key-on wakeup selection bit, enable/disable of a key-on wakeup of P00 pin can be selected. Notes on use When setting the followings, the interrupt request bit may be set to "1". *When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit) to "1". Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). Interrupt request generating conditions At reset input At completion of serial I/O data receive At completion of serial I/O transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer X underflow Not available Not available At timer A underflow Not available At completion of A/D conversion At timer 1 underflow Not available At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) External interrupt (active edge selectable) External interrupt (active edge selectable) STP release timer underflow Non-maskable software interrupt Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 19 of 66 7544 Group Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Fig. 19 Interrupt control Interrupt request b7 b0 Interrupt edge selection register (INTEDGE : address 003A16, initial value : 0016) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Disable (returns "0" when read) P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt request register 2 (IREQ2 : address 003D16, initial value : 0016) Disable (returns "0" when read) Disable (returns "0" when read) Timer A interrupt request bit Disable (returns "0" when read) A/D conversion interrupt request bit Timer 1 interrupt request bit Disable (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer X interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 2 (ICON2 : address 003F16, initial value : 0016) Disable (returns "0" when read) Disable (returns "0" when read) Timer A interrupt enable bit Disable (returns "0" when read) A/D conversion interrupt enable bit Timer 1 interrupt enable bit Disable (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 20 Structure of Interrupt-related registers Rev.1.04 2004.06.08 REJ03B0012-0104Z page 20 of 66 7544 Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports. Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch Falling edge detection Port P07 Direction register = "1" Key input interrupt request PULL register bit 3 = "0" * P06 output ** Port P06 latch Port P06 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P05 output ** Port P05 latch Port P05 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P04 output ** Port P04 latch Port P04 Direction register = "1" Falling edge detection PULL register bit 2 = "1" * P03 input ** Port P03 latch Port P03 Direction register = "0" Port P0 Input read circuit Falling edge detection PULL register bit 2 = "1" * P02 input ** Port P02 latch Port P02 Direction register = "0" Falling edge detection PULL register bit 1 = "1" * P01 input ** Port P01 latch Port P01 Direction register = "0" Falling edge detection PULL register bit 0 = "1" * P00 input Port P00 key-on wakeup selection bit ** Port P00 latch Port P00 Direction register = "0" Falling edge detection * P-channel transistor for pull-up ** CMOS output buffer Fig. 21 Connection example when using key input interrupt and port P0 block diagram Rev.1.04 2004.06.08 REJ03B0012-0104Z page 21 of 66 7544 Group Timers The 7544 Group has 3 timers: timer 1, timer A and timer X. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1". Timer A Timer A is a 16-bit timer and counts the signal selected by the timer A count source selection bit. When Timer A underflows, the timer A interrupt request bit is set to "1". Timer A consists of the low-order of Timer A (TAL) and the high-order of Timer A (TAH). Timer A has the timer A latch to retain the reload value. The value of timer A latch is set to Timer A at the timing shown below. * When Timer A undeflows. * When an active edge is input from CNTR1 pin (valid only when period measurement mode and pulse width HL continuously measurement mode). When writing to both the low-order of Timer A (TAL) and the highorder of Timer A (TAH) is executed, the value is written to both the timer A latch and Timer A. When reading from the low-order of Timer A (TAL) and the high-order of Timer A (TAH) is executed, the following values are read out according to the operating mode. * In timer mode, event counter mode: The count value of Timer A is read out. * In period measurement mode, pulse width HL continuously measurement mode: The measured value is read out. Be sure to write to/read out the low-order of Timer A (TAL) and the high-order of Timer A (TAH) in the following order; Read Read the high-order of Timer A (TAH) first, and the low-order of Timer A (TAL) next and be sure to read out both TAH and TAL. Write Write to the low-order of Timer A (TAL) first, and the high-order of Timer A (TAH) next and be sure to write to both TAL and TAH. Timer A can be selected in one of 4 operating modes by setting the timer A mode register. (1) Timer mode Timer A counts the selected by the timer A count source selection bit. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach "000016", an underflow occurs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of Timer A is 1/(n+1) provided that the value of Timer A is n. (2) Period measurement mode In the period measurement mode, the pulse period input from the P00/CNTR1 pin is measured. CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in the timer A latch is reloaded in Timer A and count continues. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit .The count value when trigger input from CNTR1 pin is accepted is retained until Timer A is read once. Timer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to "1". Prescaler 1 is an 8-bit prescaler and counts the signal selected by the timer 1 count source selection bit. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows. The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal selected by the timer 1 count source selection bit. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach "0016", an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach "0016", an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)(m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 22 of 66 7544 Group (3) Event counter mode Timer A counts signals input from the P00/CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit . (4) Pulse width HL continuously measurement mode In the pulse width HL continuously measurement mode, the pulse width ("H" and "L" levels) input to the P00/CNTR1 pin is measured. CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. The count value when trigger input from the CNTR1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting "1" to the timer A count stop bit in any mode. Also, when Timer A underflows, the timer A interrupt request bit is set to "1". Note on Timer A is described below; Note on Timer A CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is "0", the CNTR1 interrupt request bit is set to "1" at the falling edge of the CNTR1 pin input signal. When this bit is "1", the CNTR1 interrupt request bit is set to "1" at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. b7 b0 Timer A mode register (TAM : address 001D16, initial value: 0016) Disable (return "0" when read) Timer A operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer A count stop bit 0 : Count start 1 : Count stop Fig. 22 Structure of timer A mode register b7 b0 Timer count source set register 2 (TCSS2 : address 002F16, initial value: 0016) Timer 1 count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output 1 1 : Disable Timer A count source selection bits b3 b2 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output 1 1 : Disable Disable (return "0" when read) Note : System operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. Fig. 23 Timer count source set register 2 Rev.1.04 2004.06.08 REJ03B0012-0104Z page 23 of 66 7544 Group Timer X Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to "1". Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows. The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) and Timer X (TX) is executed, writing to "latch only" or "latch and prescaler (timer)" can be selected by the setting value of the timer X write control bit. When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out. Timer X can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach "0016", an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach "0016", an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1)(m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is "0", the output of CNTR0 pin is started at "H" level. When this bit is "1", the output is started at "L" level. Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting "1" to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. (3) Event counter mode The timer A counts signals input from the P14/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit . (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "H". The count is stopped while the pin is "L". Also, when the CNTR0 active edge switch bit is "1", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "L". The count is stopped while the pin is "H". Timer X can stop counting by setting "1" to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". Note on Timer X is described below; Note on Timer X CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 24 of 66 7544 Group b7 b0 Timer X mode register (TXM : address 002B16, initial value: 0016) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR0 output) Disable (return "0" when read) Fig. 24 Structure of timer X mode register b7 b0 Timer count source set register 1 (TCSS1 : address 002E16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note) 1 1 : Not available Disable (return "0" when read) Note : f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. Fig. 25 Timer count source set register 1 Rev.1.04 2004.06.08 REJ03B0012-0104Z page 25 of 66 7544 Group Data bus Prescaler 1 latch (8) Timer 1 latch (8) f(XIN)/16 f(XIN)/2 On-chip oscillator clock RING Prescaler 1 (8) Pulse width HL continuously measurement mode Rising edge detected Timer 1 (8) Timer 1 interrupt request bit Period measurement mode Falling edge detected P00/CNTR1 CNTR1 active edge switch bit Data bus Timer A (low-order) latch (8) Timer A (high-order) latch (8) Timer A (low-order) (8) f(XIN)/16 f(XIN)/2 On-chip oscillator clock RING Timer A count stop bit Timer A (high-order) (8) Timer A interrupt request bit Timer A operation mode bit Fig. 26 Block diagram of timer 1 and timer A Data bus f(XIN)/16 f(XIN)/2 f(XIN) Timer X count source selection bits Prescaler X latch (8) Pulse width Timer mode measurement Pulse output mode mode Prescaler X (8) Timer X latch (8) Timer X (8) P14/CNTR0 CNTR0 active edge switch bit "0" Event counter mode Timer X interrupt request bit Timer X count stop bit CNTR0 interrupt request bit Q Q Toggle flip-flop T R Timer X write control bit Writing to timer X latch Pulse output mode "1" CNTR0 active "1" edge switch bit Port P14 direction register Pulse output mode P03/TXOUT Port P14 latch "0" Port P03 latch P03/TXOUT output valid Port P03 direction register Fig. 27 Block diagram of timer X Rev.1.04 2004.06.08 REJ03B0012-0104Z page 26 of 66 7544 Group Serial I/O Serial I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register (bit 6) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Address 001816 Receive buffer register P10/RXD Receive shift register Shift clock P12/SCLK Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 Clock control circuit Shift clock P11/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916 Serial I/O status register Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit XIN BRG count source selection bit 1/4 P13/SRDY F/F Falling-edge detector Fig. 28 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 29 Operation of clock synchronous serial I/O function Rev.1.04 2004.06.08 REJ03B0012-0104Z page 27 of 66 7544 Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register OE Character length selection bit Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P10/RXD ST detector 7 bits 8 bits Receive shift register PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O synchronous clock selection bit P12/SCLK BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P11/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) XIN Fig. 30 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1 Serial output TXD ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 31 Operation of UART serial I/O function Rev.1.04 2004.06.08 REJ03B0012-0104Z page 28 of 66 7544 Group [Transmit buffer register/receive buffer register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O status register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O control register (SIOCON)] 001A16 The serial I/O control register consists of eight control bits for the serial I/O function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Notes on serial I/O * Serial I/O interrupt When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled). * I/O pin function when serial I/O is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O mode selection bit and a serial I/O synchronous clock selection bit as follows. (1) Serial I/O mode selection bit "1" : Clock synchronous type serial I/O is selected. Setup of a serial I/O synchronous clock selection bit "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY output enable bit (SRDY) "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY output pin. (2) Serial I/O mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O synchronous clock selection bit "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 29 of 66 7544 Group b7 b0 Serial I/O status register (SIOSTS : address 001916, initial value: 0016) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Disable (returns "1" when read) b7 b0 Serial I/O control register (SIOCON : address 001A16, initial value: 0016) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P13 pin operates as ordinary I/O pin 1: P13 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P10 to P13 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P10 to P13 operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B16, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Disable (return "1" when read) Fig. 32 Structure of serial I/O-related registers Rev.1.04 2004.06.08 REJ03B0012-0104Z page 30 of 66 7544 Group A/D Converter The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A/D conversion, and changes to "1" at completion of A/D conversion. A/D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P25/AN5 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A/D conversion. b7 b0 A/D control register (ADCON : address 003416, initial value: 1016) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : Disable 111 : Disable Disable (returns "0" when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Disable (returns "0" when read) Fig. 33 Structure of A/D control register Notes on A/D converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500 kHz or more during A/D conversion. As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.. (2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Data bus b7 A/D control register (Address 003416) 3 A/D control circuit P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 b0 A/D interrupt request Channel selector P20/AN0 Comparator A/D conversion register (low-order) 10 Resistor ladder (Address 003516) VREF VSS Fig. 34 Block diagram of A/D converter Rev.1.04 2004.06.08 REJ03B0012-0104Z page 31 of 66 7544 Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 003916), the watchdog timer H is set to "FF16" and the watchdog timer L is set to "FF16". Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is "0", the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz. When this bit is "1", the count source becomes f(XIN)/16. In this case, the detection time is 512 s at f(XIN)=8 MHz. This bit is cleared to "0" after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset. Data bus Write "FF16" to the watchdog timer control register Watchdog timer L (8) 1/16 Write "FF16" to the watchdog timer control register "0" "1" Watchdog timer H (8) XIN Watchdog timer H count source selection bit STP Instruction disable bit STP Instruction Reset circuit Internal reset RESET Fig. 35 Block diagram of watchdog timer b7 b0 Watchdog timer control register (WDTCON: address 003916, initial value: 3F16) Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 Fig. 36 Structure of watchdog timer control register Rev.1.04 2004.06.08 REJ03B0012-0104Z page 32 of 66 7544 Group Reset Circuit The microcomputer is put into a reset status by holding the RESET pin at the "L" level for 2 s or more when the power source voltage is 4.5 to 5.5 V and XIN is in stable oscillation. ______ After that, this reset status is released by returning the RESET pin to the "H" level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. In the case of f() 8 MHz, the reset input voltage must be 0.9 V or less when the power source voltage passes 4.5 V. RESET VCC Power source voltage 0V Reset input voltage 0V Poweron (Note) 0.2 VCC Note : Reset release voltage Vcc 4.5V RESET VCC Power source voltage detection circuit Fig. 37 Example of reset circuit Clock from on-chip oscillator RING RESET RESETOUT SYNC Address Data ? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD ADH,ADL ADH Reset address from the vector table 8-13 clock cycles Notes 1 : An on-chip oscillator applies about RING*2 MHz, *250 kHz frequency clock at average of Vcc = 5 V. 2 : The mark "?" means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET. Fig. 38 Timing diagram at reset Rev.1.04 2004.06.08 REJ03B0012-0104Z page 33 of 66 7544 Group Address (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Pull-up control register Port P1P3 control register Serial I/O status register Serial I/O control register UART control registe 000116 000316 000516 000716 001616 001716 001916 001A16 001B16 001D16 001E16 001F16 002816 002916 002B16 002C16 002D16 002E16 002F16 003416 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) X : Undefined X X 1 0 0 0 0 0 0 0 1 1 1 0 X X 0 Register contents 0016 X X X X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016 0016 0 0 0 0 0 0 0016 1 0 0 0 0 0 (10) Timer A mode register (11) Timer A (low-order) (12) Timer A (high-order) (13) Prescaler 1 (14) Timer 1 (15) Timer X mode register (16) Prescaler X (17) Timer X (18) Timer count source set register 1 (19) Timer count source set register 2 (20) A/D control register (21) MISRG (22) Watchdog timer control register (23) Interrupt edge selection register (24) CPU mode register (25) Interrupt request register 1 (26) Interrupt request register 2 (27) Interrupt control register 1 (28) Interrupt control register 2 (29) Processor status register (30) Program counter 0016 FF16 FF16 FF16 0 0 0 0 0 1 0016 FF16 FF16 0016 0016 0 1 0 0 0 0 0016 1 1 1 1 1 1 0016 0 0 0 0 0 0 0016 0016 0016 0016 X X X 1 X X Contents of address FFFD16 Contents of address FFFC16 The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set bifore you use it. Fig. 39 Internal status of microcomputer at reset Rev.1.04 2004.06.08 REJ03B0012-0104Z page 34 of 66 7544 Group Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. XIN M37544 (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VCC and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Ceramic resonator and quartz-crystal oscillator When the ceramic resonator and quartz-crystal oscillator is used for the main clock, connect the ceramic/quartz-crystal oscillator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. (3) RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. (4) External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable freXOUT quencies and obtain the sufficient margin. Open Fig. 40 Processing of XIN and XOUT pins at on-chip oscillator operation Note: Externally connect a M37544 XIN XOUT Rd CIN COUT damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value because constants such as capacitance depend on the resonator. Fig. 41 External circuit of ceramic resonator and quartz-crystal oscillator Note: M37544 XIN XOUT R C Connect the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Fig. 42 External circuit of RC oscillation M37544 XIN XOUT Open External oscillation circuit VCC VSS Fig. 43 External clock input circuit Rev.1.04 2004.06.08 REJ03B0012-0104Z page 35 of 66 7544 Group (1) Oscillation control * Stop mode When the STP instruction is executed, the internal clock stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 1 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 1 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. Single selected by the timer 1 count source selection bit is connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock is supplied. This is because when a ceramic/quartz-crystal oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So ap______ ply an "L" level to the RESET pin while oscillation becomes stable. Also, the STP instruction cannot be used while CPU is operating by an on-chip oscillator. * Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. * Switch of ceramic/quartz-crystal and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic/quartz-crystal oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. * Double-speed mode When a ceramic/quartz-crystal oscillation is selected, a doublespeed mode can be used. Do not use it when an RC oscillation is selected. * CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU "M37544RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. * Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 48 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 48. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 8016) Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 01 Not available 10 11 Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic/quartz-crystal or RC oscillation enabled 1 : Ceramic/quartz-crystal or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic/quartz-crystal oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f() = f(XIN) (Double-speed mode)(Note 2) Note 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37544RSS".) 2: These bits are used only when a ceramic/quartz-crystal oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 44 Structure of CPU mode register Rev.1.04 2004.06.08 REJ03B0012-0104Z page 36 of 66 7544 Group Oscillation stop detection circuit The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by disconnection. When internal reset occurs, reset because of oscillation stop can be detected by setting "1" to the oscillation stop detection status bit. Also, when using the oscillation stop detection circuit, an on-chip oscillator is required. Figure 48 shows the state transition. The oscillation stop detection status bit retains "1", not initialized, when the oscillation stop reset occurs. The oscillation stop detection status bit is initialized to "0" when the external reset occurs. Accordingly, reset by oscillation stop can be confirmed by using this bit. Notes on Oscillation Stop Detection Circuit * Oscillation stop detection status bit is initialized by the following operation. (1) External reset (2) Write "0" data to the ceramic or RC oscillation stop detection function active bit. * The oscillation stop detection circuit is not included in the emulator MCU "M37544RSS". b7 b0 MISRG(address 003816, initial value: 0016) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 1 automatically 1: Not set automatically Ceramic/quartz-crystal or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Reserved bits (return "0" when read) (Do not write "1" to these bits) Disable (return "0" when read) Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Fig. 45 Structure of MISRG Rev.1.04 2004.06.08 REJ03B0012-0104Z page 37 of 66 7544 Group XIN Rf XOUT Clock division ratio selection bit Middle-, high-, low-speed mode 1/2 On-chip oscillator mode 1/4 1/2 Prescaler 1 Clock division ratio selection bit Middle-speed mode Timer 1 High-speed mode RING On-chip oscillator Double-speed mode Timing (Internal clock) 1/8 On-chip oscillator mode QS R STP instruction WIT instruction S R Q Q S R STP instruction RESET Reset Interrupt disable flag l Interrupt request Fig. 46 Block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator) XOUT XIN Clock division ratio selection bit Middle-, high-, low-speed mode 1/2 On-chip oscillator mode 1/4 1/2 Prescaler 1 Timer 1 Delay Clock division ratio selection bit Middle-speed mode High-speed mode RING On-chip oscillator Double-speed mode Timing (Internal clock) 1/8 On-chip oscillator mode QS R STP instruction WIT instruction S R Q Q S RESET R STP instruction Reset Interrupt disable flag l Interrupt request Fig. 47 Block diagram of internal clock generating circuit (for RC oscillation) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 38 of 66 7544 Group Stop mode Interrupt Interrupt STP instruction Wait mode WIT instruction Interrupt WIT instruction State 2 CPUM76102 State 1 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator stop CPUM302 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled CPUM312 On-chip oscillator enabled State 3 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled State 4 CPUM412 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation stop CPUM402 On-chip oscillator enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) MISRG112 MISRG102 MISRG112 MISRG102 State 2' Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76102 CPUM76002 012 On-chip oscillator enabled 112 (Note 2) State 3' Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (high-speed mode) f(XIN)/8 (middle-speed mode) f(XIN) (double-speed mode, only at a ceramic/quartz-crystal oscillation) (2) Execute the state transition state 3 to state 2 or state 3' to state 2' after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 state 3 state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. * CPUM76 102 (State 2 state 3) * NOP instruction * CPUM4 12 (State 3 state 4) Double-speed mode at on-chip oscillator: NOP 3 High-speed mode at on-chip oscillator: NOP 1 Middle-speed mode at on-chip oscillator: NOP 0 Oscillation stop detection circuit valid Reset released Reset state Fig. 48 State transition Rev.1.04 2004.06.08 REJ03B0012-0104Z page 39 of 66 7544 Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. State transition Do not stop the clock selected as the operation clock because of setting of CM3, 4. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. Decimal Calculations * For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form * 2.Mark Specification Form * For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/en/rom). Ports * The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic / quartz-crystal oscillation is selected, a doublespeed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 40 of 66 7544 Group NOTES ON USE Countermeasures against noise 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. (3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. DIP SDIP SOP QFP Noise XIN XOUT VSS N.G. Fig. 51 Wiring for clock I/O pins XIN XOUT VSS O.K. Fig. 49 Selection of packages (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). (4) Wiring to CNVss pin Connect the CNVss pin to the Vss pin with the shortest possible wiring. Noise Noise Reset circuit VSS N.G. RESET VSS CNVSS VSS CNVSS VSS N.G. Reset circuit VSS RESET VSS Fig. 52 Wiring for CNVss pin O.K. O.K. Fig. 50 Wiring for the RESET pin Rev.1.04 2004.06.08 REJ03B0012-0104Z page 41 of 66 7544 Group (5) Wiring to VPP pin of One Time PROM version Connect an approximately 5 k resistor to the VPP pin the shortest possible in series and also to the Vss pin. When not connecting the resistor, make the length of wiring between the VPP pin and the Vss pin the shortest possible. Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. 3. Wiring to analog input pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin. Besides, connect the capacitor to the Vss pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. Noise About 5k CNVSS/VPP VSS shortest distance (Note) Microcomputer Analog input pin N.G. O.K. Thermistor Fig. 53 Wiring for the VPP pin of the One Time PROM 2. Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. VSS Note : The resistor is used for dividing resistance with a thermistor. Fig. 55 Analog signal line and a resistor and a capacitor * The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. VCC VCC VSS VSS N.G. O.K. Fig. 54 Bypass capacitor across the VSS line and the VCC line Rev.1.04 2004.06.08 REJ03B0012-0104Z page 42 of 66 7544 Group 4. Oscillator concerns So that the product obtains the stabilized operation clock on the user system and its condition, contact the resonator manufacturer and select the resonator and oscillation circuit constants. Be careful especially when range of voltage and temperature is wide. Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. (3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 57 Vss pattern on the underside of an oscillator Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M Large current GND Installing oscillator away from signal lines where potential levels change frequently XIN XOUT VSS N.G. Do not cross CNTR XIN XOUT VSS Fig. 56 Wiring for a large current signal line/Writing of signal lines where potential levels change frequently Rev.1.04 2004.06.08 REJ03B0012-0104Z page 43 of 66 7544 Group 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: O.K. Noise Data bus Direction register N.G. Port latch I/O port pins Noise Main routine Fig. 58 Setup for I/O ports 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine errors (SWDT) N CLI Main processing N (SWDT) =N? N Interrupt processing routine errors Fig. 59 Watchdog timer by software 7. Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between the mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One Time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 44 of 66 7544 Group PROM Mode M37544G2SP/GP (referred to as "the MCU") has a PROM Mode as well as the normal operation mode. PROM Mode enables an external device (referred to as "Programmer") to read and program the built-in EPROM via a minimum number of serial I/O pins by sending commands to control the MCU. To enable PROM Mode, use the pin connection shown in Figure 60 to 61 and apply power (VCC). Then execute the new OTP entry operation, called "Mad Dog Entry". There are three operation modes in PROM Mode : Read, Program and Program-Verify. Three commands are defined to enable each mode respectively. The format of the serial I/O is : clock synchronous and LSB-datafirst. ESCLK RESETB VPP VCC XIN XOUT VSS P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P11/TXD P10/RXD P07(LED7) P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 P37(LED13)/INT0 P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8) ESDA ESPGMB M37544G2SP Fig. 60 "Mad Dog Entry" Pin Diagram (32P4B) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 45 of 66 7544 Group 23 20 18 22 24 ESPGMB ESDA ESCLK P07(LED7) P10/RXD P11/TXD P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1 21 19 17 P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 P37(LED13)/INT0 25 26 27 28 29 30 31 32 1 3 2 4 5 6 7 8 16 15 14 M37544G2GP 13 12 11 10 9 P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8) VSS VSS XOUT XOUT XIN XIN Fig. 61 "Mad Dog Entry" Pin Diagram (32P6U-A) Rev.1.04 2004.06.08 REJ03B0012-0104Z page 46 of 66 RESETB VPP VCC P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 7544 Group Precaution for Handling One-Time-Programmable Devices Our company ships one-time-programmable version MCUs (OneTime PROM MCU) without being screened by the PROM writing test. To ensure the reliability of the MCU, We recommend that the user performs the program and test procedure shown in Figure 62 before using the MCU. Programming with PROM programmer Screening (Caution) (150 C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 62 Programming and testing of One Time PROM Rev.1.04 2004.06.08 REJ03B0012-0104Z page 47 of 66 7544 Group ROM Code Access Protection We would like to support a simple ROM code protection function that prevents a party other than the ROM-code owner to read and reprogram the builit-in PROM code of the MCU. The MCU has 7 bytes of dedicated ROM spaces in address 0xFFD4 to 0xFFDA, as an ID-code (referred to as "the ID-code") enabling a Programmer to verify with the input ID-code and validate further operations. Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Expected Programmer ID-Code Verification Function First, Programmer must check the ID-code of the MCU. If the ID-code is still in blank, Programmer enables all operations, Read, Program, and Program-Verify. When Programmer programs the MCU, Programmer also programs the given ID-code as well as the actual firmware. If the ID-code is not blank, Programmer verifies it with the input ID-code. When the ID-codes don't match, Programmer will reject all further operations. If they match, Programmer perform operations according to the given command. Fig. 63 ROM-Code Protection ID Location Rev.1.04 2004.06.08 REJ03B0012-0104Z page 48 of 66 7544 Group ELECTRICAL CHARACTERISTICS 1.7544Group Applied to: M37544M2-XXXSP/GP/HP, M37544G2SP/GP/HP(Note) Note: M37544G2HP: Only ES version (MP: no plan) Absolute Maximum Ratings Table 9 Absolute maximum ratings Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P14, P20-P25, P30-P34,P37, VREF ______ Input voltage RESET, XIN Input voltage CNVSS (Note) Output voltage P00-P07, P10-P14, P20-P25, P30-P34,P37, XOUT Power dissipation Operating temperature Storage temperature Ta = 25C 200 -20 to 85 -40 to 125 mW C C All voltages are based on VSS. Output transistors are cut off. Conditions Ratings -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 7.0 -0.3 to VCC + 0.3 Unit V V V V V Notes : It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 49 of 66 7544 Group Recommended Operating Conditions Table 10 Recommended operating conditions (1) (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC Power source voltage (ceramic) Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage P00-P07, P10-P14, P20-P25, P30-P34, P37 "H" input voltage (TTL input level selected) P10, P12, P34, P37 "H" input voltage ______ RESET, XIN "L" input voltage P00-P07, P10-P14, P20-P25, P30-P34, P37 "L" input voltage (TTL input level selected) P10, P12, P34, P37 "L" input voltage ______ RESET, CNVSS "L" input voltage XIN "H" total peak output current (Note) P00-P07, P10-P14, P20-P25, P30-P34, P37 "L" total peak output current (Note) P10-P14, P20-P25 "L" total peak output current (Note) P00-P07, P30-P34, P37 "H" total average output current (Note) P00-P07, P10-P14, P20-P25, P30-P34, P37 "L" total average output current (Note) P10-P14, P20-P25 "L" total average output current (Note) P00-P07, P30-P34, P37 30 mA 40 mA 60 -40 mA mA 80 mA 0 0 0.2VCC 0.16VCC -80 V V mA 0.8VCC 0 0 VCC 0.3VCC 0.8 V V V 2.0 0.8VCC 2.0 Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 8 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) Limits Min. 4.0 4.5 4.0 Typ. 5.0 5.0 5.0 0 VCC VCC VCC Max. 5.5 5.5 5.5 Unit V V V V V V V Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 50 of 66 7544 Group Recommended Operating Conditions (continued) Table 11 Recommended operating conditions (2) (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Parameter "H" peak output current (Note 1) P00-P07, P10-P14, P20-P25, P30-P34, P37 "L" peak output current (Note 1) P10-P14, P20-P25 "L" peak output current (Note 1) P00-P07, P30-P34, P37 "H" average output current (Note 2) P00-P07, P10-P14, P20-P25, P30-P34, P37 "L" average output current (Note 2) P10-P14, P20-P25 "L" average output current (Note 2) P00-P07, P30-P34, P37 Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. 8 8 4 MHz MHz MHz 15 mA -5 5 mA mA 30 mA Min. Typ. Max. -10 10 Unit mA mA Rev.1.04 2004.06.08 REJ03B0012-0104Z page 51 of 66 7544 Group Electrical Characteristics Table 12 Electrical characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol VOH Parameter Test conditions Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 0.4 Typ. Max. Unit V V V V V V V V V "H" output voltage IOH = -5 mA P00-P07, P10-P14, P20-P25, P30-P34, P37 (Note 1) VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 4.0 to 5.5 V VOL "L" output voltage P10-P14, P20-P25 IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 4.0 to 5.5 V VOL "L" output voltage P00-P07, P30-P34, P37 IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V VT+-VT- Hysteresis CNTR0, CNTR1, INT0, INT1 (Note 2) P00-P07 (Note 3) Hysteresis RXD, SCLK (Note 2) Hysteresis ______ RESET "H" input current P00-P07, P10-P14, P20-P25, P30-P34, P37 "H" input current ______ RESET "H" input current XIN "L" input current P00-P07, P10-P14, P20-P25, P30-P34, P37 "L" input ______ current RESET, CNVSS "L" input current XIN "L" input current P00-P07, P30-P34, P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped VCC = 5.0 V, Ta = 25 C VCC = 5.0 V, Ta = 25 C 2.0 1000 62.5 2000 125 -4.0 -0.2 -0.5 5.5 3000 187.5 4.0 -5.0 VT+-VT- VT+-VT- IIH 0.5 0.9 5.0 V V A IIH IIH IIL 5.0 A A A IIL IIL IIL VRAM ROSC DOSC -5.0 A A mA V kHz kHz Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD, SCLK, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 52 of 66 7544 Group Electrical Characteristics (continued) Table 13 Electrical characteristics (2) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol ICC Parameter Power source current Test conditions High-speed mode, f(XIN) = 8 MHz Output transistors "off" Double-speed mode, f(XIN) = 8 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode(in WIT state), VCC = 5V functions except timer 1 disabled, Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C Min. Typ. 3.3 4.8 1.8 250 1.3 Max. 8.0 10.0 5.0 900 3.2 Unit mA mA mA A mA 140 450 A 0.45 0.1 1.0 10.0 mA A A Rev.1.04 2004.06.08 REJ03B0012-0104Z page 53 of 66 7544 Group A/D Converter Characteristics Table 14 A/D Converter characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol -- ABS tCONV RLADDER IVREF II(AD) Resolution Absolute accuracy (quantification error excluded) Conversion time Ladder resistor Reference power source input current A/D port input current VREF = 5.0 V VREF = 3.0 V 50 30 37 135 80 200 120 5.0 A Ta = -20 to 85 C, Vcc = VREF Parameter Test conditions Limits Min. Typ. Max. 8 3 109 Unit Bits LSB tc(XIN) k A Note: As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.. (2) When VREF voltage is less than [ 3.0V ], the accuracy at the time of low temperature may become extremely low compared with the time of room temperature. The use beyond VREF=3.0V is recommended in the system the use by the side of low temperature is assumed to be. Timing Requirements Table 15 Timing requirements (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ______ tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Limits Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 54 of 66 7544 Group Switching Characteristics Table 16 Switching characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TxD) tv(SCLK-TxD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note) CMOS output falling time (Note) 10 10 -30 30 30 30 30 Limits Min. tC(SCLK)/2-30 tC(SCLK)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns Note : Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Fig. 64 Switching characteristics measurement circuit diagram Rev.1.04 2004.06.08 REJ03B0012-0104Z page 55 of 66 7544 Group tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC CNTR0 0.8VCC tC(CNTR1) tWH(CNTR1) tWL(CNTR1) 0.2VCC CNTR1 0.8VCC tWH(CNTR0) tWL(CNTR0) 0.2VCC INT0, INT1 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(SCLK) tf tWL(SCLK) 0.2VCC tsu(RxD-SCLK) tr 0.8VCC tWH(SCLK) SCLK th(SCLK-RxD) RXD (at receive) td(SCLK-TxD) 0.8VCC 0.2VCC tv(SCLK-TxD) TXD (at transmit) Fig. 65 Timing chart Rev.1.04 2004.06.08 REJ03B0012-0104Z page 56 of 66 7544 Group PACKAGE OUTLINE 32P4B EIAJ Package Code SDIP32-P-400-1.78 Recommended JEDEC Code - Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy Plastic 32pin 400mil SDIP 32 17 1 16 D Symbol A A1 A2 b b1 b2 c D E e e1 L e SEATING PLANE b1 b b2 Dimension in Millimeters Min Nom Max - - 5.08 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 - 1.778 - - 10.16 - 3.0 - - 0 - 15 A 32P6U-A L Recommended JEDEC Code - HD D 32 25 A1 A2 Plastic 32pin 77mm body LQFP Weight(g) Lead Material Cu Alloy e EIAJ Package Code LQFP32-P-0707-0.80 MD e1 E c I2 1 24 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 8 17 9 16 E HE A L1 A2 A3 e F A1 L Lp b c x y b2 I2 MD ME x M y Detail F Rev.1.04 2004.06.08 REJ03B0012-0104Z page 57 of 66 b2 Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.32 0.37 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 - 0.8 - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.6 0.45 0.75 - 0.25 - - - 0.2 - - 0.1 - 0 10 0.5 - - 1.0 - - 7.4 - - - - 7.4 ME 7544 Group 36PJW-A EIAJ Package Code WQFN36-P-0606-0.50 JEDEC Code - Weight(g) 0.83 Lead Material Cu Alloy Plastic 36pin 6X6mm body WQFN MD e I2 D 27 28 19 18 4.26 (Typ.) c 18 19 27 28 Recommended Mount Pad e 4.26 (Typ.) E y Symbol 36 1 9 10 10 9 1 36 A Lp b x M A b c D E e Lp x y b2 I2 MD ME Rev.1.04 2004.06.08 REJ03B0012-0104Z page 58 of 66 b2 Dimension in Millimeters Min Nom Max - - 0.8 0.2 0.15 0.25 - - 0.2 5.9 6.1 6.0 5.9 6.1 6.0 - - 0.5 0.5 0.6 0.7 - - 0.05 - - 0.05 0.3 - - 0.7 - - 4.8 - - - 4.8 - ME 7544 Group APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized to "1" before each calculation. Set D flag to "1" ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Fig. 4 Status flag at decimal calculations 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. BRK instruction (1) Interrupt priority level When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority. * Interrupt request bit and interrupt enable bit are set to "1". * Interrupt disable flag (I) is set to "1" to disable interrupt. 5. Multiplication and Division Instructions (1) The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. (2) The execution of these instructions does not change the contents of the processor status register. Reset Initializing of flags Main program Fig. 1 Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction should be executed after every PLP instruction. PLP instruction execution NOP Fig. 2 Sequence of PLP instruction execution (S) (S)+1 Stored PS Fig. 3 Stack memory contents after PHP instruction execution Rev.1.04 2004.06.08 REJ03B0012-0104Z page 59 of 66 7544 Group 6. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (SFR). The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family. (1) Bit management instructions: CLB, SEB (2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF (3) Add and subtract instructions: DEC, INC (4) Logical operation instructions (1's complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = "1" operate in the way as the readmodify-write instruction. Do not execute the read invalid SFR. 3. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. NOTES ON PERIPHERAL FUNCTIONS Notes on I/O Ports 1. Pull-up control register When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. 4. Direction register The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read-modify-write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 60 of 66 7544 Group Termination of Unused Pins 1. Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) I/O ports Set the I/O ports for the input mode and connect each pin to VCC or VSS through each resistor of 1 k to 10 k. The port which can select a built-in pull-up resistor can also use the built-in pull-up resistor. When using the I/O ports as the output mode, open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. Termination remarks (1) I/O ports setting as input mode [1] Do not open in the input mode. Notes on Interrupts 1. Change of relevant register settings When not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in Figure 5. * When switching external interrupt active edge * When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Set the corresponding interrupt enable bit to "0" (disabled) . Set the interrupt edge selection bit, active edge switch bit, or the interrupt source selection bit. NOP (One or more instructions) Set the corresponding interrupt request bit to "0" (no interrupt request issued). Set the corresponding interrupt enable bit to "1" (enabled). Fig. 5 Sequence of changing relevant register Set the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Fig. 6 Sequence of check of interrupt request bit Rev.1.04 2004.06.08 REJ03B0012-0104Z page 61 of 66 7544 Group Notes on Timers 1. When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). 2. When a count source of timer X is switched, stop a count of the timer. Notes on Timer X 1. CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit (bit 2 of timer X mode register (address 2B16)). When this bit is "0", the CNTR0 interrupt request bit goes to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit goes to "1" at the rising edge of CNTR0 pin input signal. 2. Timer X count source selection The f(XIN) (frequency not divided) can be selected by the timer X count source selection bits (bits 1 and 0 of timer count source set register 1 (address 2E16)) only when the ceramic oscillation or the on-chip oscillator is selected. Do not select it for the timer X count source at the RC oscillation. 3. Pulse output mode Set the direction register of port P14, which is also used as CNTR0 pin, to output. When the TXOUT pin is used, set the direction register of port P03, which is also used as TXOUT pin, to output. 4. Pulse width measurement mode Set the direction register of port P14, which is also used as CNTR0 pin, to input. Notes on Timer 1 1. Timer 1 count source The "on-chip oscillator output" of timer 1 count source selection bits (bits 1 and 0 of timer count source set register 2 (address 2F16)) can be selected while the on-chip oscillator oscillation control bit (bit 3 of CPU mode register (address 3B16)) is "0" (on-chip oscillator oscillation enabled). Notes on Timer A 1. CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit (bit 6 of timer A mode register (address 1D16)). When this bit is "0", the CNTR1 interrupt request bit goes to "1" at the falling edge of the CNTR1 pin input signal. When this bit is "1", the CNTR1 interrupt request bit goes to "1" at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 2. Period measurement mode, event counter mode and pulse width HL continuously measurement mode Set the direction register of port P00, which is also used as CNTR1 pin, to input. Set the key-on wakeup function of P00, which is also used as CNTR1 pin, to be disabled by setting the P00 key-on wakeup selection bit (bit 7 of interrupt edge selection register (address 3A16)) to "1". 3. Timer A count source The "on-chip oscillator output" of timer A count source selection bits (bits 3 and 2 of timer count source set register 2 (address 2F16)) can be selected while the on-chip oscillator oscillation control bit (bit 3 of CPU mode register (address 3B16)) is "0" (on-chip oscillator oscillation enabled). Rev.1.04 2004.06.08 REJ03B0012-0104Z page 62 of 66 7544 Group Notes on Serial I/O 1. Clock synchronous serial I/O (1) When the transmit operation is stopped, clear the serial I/O enable bit (bit 7) and the transmit enable bit (bit 4 of serial I/O control register (address 1A16)) to "0" (serial I/O and transmit disabled). 3. Notes common to clock synchronous serial I/O and UART (1) Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Can be set with the LDM instruction at the same time Fig. 7 Sequence of setting serial I/O control register again (2) The transmit shift completion flag (bit 2 of serial I/O status register (address 1916)) changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (3) When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set "1" to the transmit enable bit while the SCLK is "H" state. Also, write to the transmit buffer register while the SCLK is "H" state. (4) When the transmit interrupt is used, set as the following sequence. Serial I/O transmit interrupt enable bit is set to "0" (disabled). Serial I/O transmit enable bit is set to "1". Serial I/O transmit interrupt request bit (bit 1 of interrupt request register 1 (address 3C16)) is set to "0" after 1 or more instructions have been executed. Serial I/O transmit interrupt enable bit (bit 1 of interrupt control register 1 (address 3E16)) is set to "1" (enabled). Rev.1.04 2004.06.08 REJ03B0012-0104Z page 63 of 66 7544 Group 4. I/O pin function when serial I/O is enabled. The pin functions of P12/SCLK and P13/SRDY are switched to as follows according to the setting values of a serial I/O mode selection bit (bit 6 of serial I/O control register (address 1A16)) and a serial I/O synchronous clock selection bit (bit 1 of serial I/O control register). (1) Serial I/O mode selection bit "1" : Clock synchronous type serial I/O is selected. * Setup of a serial I/O synchronous clock selection bit "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. * Setup of a SRDY output enable bit (SRDY) "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY output pin. (2) Serial I/O mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. * Setup of a serial I/O synchronous clock selection bit "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. * When clock asynchronous (UART) type serial I/O is selected, it functions P13 pin. It can be used as a normal I/O pin. 3. A/D conversion accuracy As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Notes on Watchdog Timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the underflow of the watchdog timer, the watchdog timer control register must be written just before executing the STP instruction. 3. The STP instruction disable bit (bit 6 of watchdog timer control register (address 3916)) can be set to "1" but cannot be set to "0" by program. Notes on A/D conversion 1. Analog input pin In order to execute the A/D conversion correctly, to complete the charge to an internal capacitor within the specified time is required. The maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; About 35 k (at f(XIN) = 8 MHz) When the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01F to 1F between an analog input pin and VSS. Further, be sure to verify the operation of application products on the user side. Notes on RESET pin 1. Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : * Make the length of the wiring which is connected to a capacitor as short as possible. * Be sure to verify the operation of application products on the user side. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 64 of 66 7544 Group Notes on Clock Generating Circuit 1. Switch of ceramic/quartz-crystal oscillation and RC oscillation After releasing reset, the oscillation mode selection bit (bit 5 of CPU mode register (address 3B16)) is "0" (ceramic/quartz-crystal oscillation selected). When the RC oscillation is used, after releasing reset, set this bit to "1". 2. Double-speed mode The double-speed mode can be used only when a ceramic oscillation is selected. Do not use it when an RC oscillation is selected. 3. CPU mode register Oscillation mode selection bit (bit 5), processor mode bits (bits 1 and 0) of CPU mode register (address 3B16) are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by erroneously writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting, it is disabled to write any data to the bit. (The emulator MCU "M37542RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB, etc.) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. 4. Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 81 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 81. 5. On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VCC through a 1 k to 10 k resistor and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that this margin of frequencies when designing application products. 6. Ceramic resonator When the ceramic resonator/quartz-crystal oscillation is used for the main clock, connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built-in. 7. RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. 8. External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Select "0" (ceramic oscillation) to oscillation mode selection bit. Notes on Oscillation Control 1. Oscillation stop detection circuit (1) When the stop mode is used, set the oscillation stop detection function to "invalid". (2) When the ceramic or RC oscillation is stopped (bit 4 of CPU mode register (address 3B16)), set the oscillation stop detection function to "invalid". (3) The oscillation stop detection circuit is not included in the emulator MCU "M37542RSS". 2. Stop mode (1) When the stop mode is used, set the oscillation stop detection function to "invalid". (2) When the stop mode is used, set "0" (STP instruction enabled) to the STP instruction disable bit of the watchdog timer control register (bit 6 of watchdog timer control register (address 3916)). (3) The oscillation stabilizing time after release of STP instruction can be selected from "set automatically"/"not set automatically" by the oscillation stabilizing time set bit after release of the STP instruction (bit 0 of MISRG (address 3816)). When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically at the execution of the STP instruction. When "1" is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. (4) The STP instruction cannot be used when the on-chip oscillator is selected by the clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)). (5) When the stop mode is used, set the on-chip oscillator oscillation control bit (bit 3 of CPU mode register (address 3B16)) to "1" (on-chip oscillator oscillation stop). (6) Do not execute the STP instruction during the A/D conversion. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 65 of 66 7544 Group Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. Rev.1.04 2004.06.08 REJ03B0012-0104Z page 66 of 66 REVISION HISTORY Rev. Date Page - 1.00 Nov. 8, 2002 1.01 May. 6, 2003 44 to 48 48 1.02 Jun. 25, 2003 7544 Group Data Sheet Description Summary First edition issued Added to Electrical Characteristics Entered to Limits Icc Power source current On-chip oscillator operation mode, On-chip oscillator operation mode(in WIT state) 49 Entered to Limits A/D Converter characteristics 6 1.03 Feb. 12, 2004 Table 2 and Fig.6: Under development eliminated. 17 [Interrupt edge selection register] added. 23 Fig.23: "1" is added to Fig. title and register name. Timer count source set register 1, TCSS1 29 Notes on A/D converter added. 33 Fig.38: Processing of XIN pin revised. 38 DATA REQUIRED FOR MASK ORDERS added. 39 Notes on A/D converter added. 47 Table 12: VOH/VOL Test conditions revised. Hysteresis RESET revised. 49 Table 14: ABS Test conditions revised. Note added. 3 Fig.4 Pin configuration : 36PJW-A added. 1.04 Jun. 08, 2004 6 Fig.7 Functional block diagram: 36PJW-A added. 8 Package: 36PJW-A added. Table 2: M37544M2-XXXHP, M37544G2HP added. "Under development" eliminated. 14 Fig.14: SIO1STS SIOSTS, SIO1CON SIOCON 23 Fig.23: Address revised. 25 Fig.25: Bit 6 revised. 31 Comparator and control circuit revised. 37 Oscillation stop detection circuit revised. 38 Fig. 46, Fig. 47 a bit name revised. 41 Countermeasure against noise added. (NOTES ON PERIPHERAL FUNCTIONS described previously here are included in APPENDIX at the end of this data sheet.) 49 Part number: M37544M2-XXXHP, M37544G2HP added. 58 PACKAGE OUTLINE: 36PJW-A added. 59 to 66 APPENDIX added. All pages Words standardized: On-chip oscillator, A/D converter (1/1) Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com (c)2002, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0 |
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